Altiumr To Xpeditionr Translator User Guide Exclusive [repack] Access

Altium footprints are converted into Xpedition Cells. It is crucial to verify that pads, solder masks, and silkscreen layers match the intended design.

Translating the schematic involves converting graphical symbols, wires, nets, and properties into Xpedition xDX Designer format. The Schematic Workflow

| | Translation Result | Solution | |---------------------|------------------------|---------------| | Parameter sets (e.g., DIFFPAIR ) | Ignored | Post-translate, assign in Xpedition CSE | | Embedded padstacks (vary by layer) | Converted to Xpedition’s default padstack | Edit each padstack in Library Manager | | Board cutouts (Polygon cutout region) | Lost; board remains solid | Recreate with Place > Board Cutout | | Net labels with leading underscore (e.g., _GND ) | Dropped (Xpedition reserves underscore) | Rename in Altium before export | | Multi-channel designs (Repeat, Room) | Flattened but component designators scrambled | Use Tools > Rename Components in Xpedition |

Altium solid planes often import as static copper. To convert them to dynamic Xpedition planes: altiumr to xpeditionr translator user guide exclusive

By preserving nets, placements, rules, and routing, these solutions empower teams to transition to the Xpedition platform without sacrificing the intellectual property embedded in their existing Altium designs. The future of PCB design lies in interoperability, and mastering the translation process is the first step toward unlocking the full potential of your new hardware ecosystem.

Xpedition requires a strict directory structure. Create a project folder with the following subdirectories before translation:

Align Altium’s routing layers (e.g., Top Layer, Internal Plane 1) with Xpedition’s defined Layer Stackup. Altium footprints are converted into Xpedition Cells

The translator works best with Binary .PcbDoc files. Hexport (ASCII) output from Altium is not recommended for Xpedition conversion.

Note: Xpedition supports IPC-2581 and ODB++; use the one you created. If only Allegro ASCII or EDIF is available, use Xpedition’s Allegro translator or import utilities.

There are two recommended approaches: neutral-format export (ODB++, IPC-2581) or direct Altium→Cadence transfer via intermediate formats (Exported Allegro ASCII or EDIF for schematic). Choose based on target Xpedition version and available import capabilities. The Schematic Workflow | | Translation Result |

| Error Message | Root Cause | Solution | | :--- | :--- | :--- | | "Unsupported primitive: Region" | Altium has a complex cutout in a polygon. | In Altium, convert polygon to separate pour outlines. | | "Netlist mismatch: 12 nets missing" | Altium PCB ASCII had unnamed copper islands. | Run Tools » Netlist » Configure in Altium; assign dummy nets to islands. | | "Padstack XYZ not in library" | Translator generated a custom pad size not in Xpedition lib. | Note the dimensions (e.g., 1.2mm round ). Create it manually in Library Manager. | | "Board outline is open loop" | Altium defined outline as multi-segment lines (not a closed polygon). | In Altium, use Design » Board Shape » Define from Selected Objects . Re-export. |

Raw Altium files often contain database structures that cause compilation failures during translation. You must optimize the source files before starting the export. 1. File Format Standardization

Siemens translators cannot parse proprietary binary Altium formats natively. Open your project in Altium Designer. File -> Save As -> Select .

| | Does NOT Translate | |----------------------------|------------------------| | Schematic sheets & symbols | ActiveScript / Delphi code | | PCB footprints & pads | 3D body definitions (STEP references only) | | Nets & connectivity | Design rule differential pairs (must be recreated) | | Basic net classes | Polygon pour order & thermal spokes | | Component parameters | Variants (BOM configurations) | | Layer stackup (physical) | Embedded BoardArray / Vias in pads |